Gen-Z Consortium Preps High-Speed Memory Interconnect

Gen-Z Consortium Preps High-Speed Memory Interconnect

Gen-Z Consortium Preps High-Speed Memory Interconnect

Sometime shortly after the turn of this decade, IT organizations should witness the arrival of servers capable of maximizing a new generation of high-speed nonvolatile memory that is supposed to begin arriving next year.

A Gen-Z Consortium formed by AMD, ARM, Cavium Inc., Cray, Dell EMC, Hewlett Packard Enterprise (HPE), Huawei, IBM, IDT, Lenovo, Mellanox Technologies, Micron, Microsemi, Red Hat, Samsung, Seagate, SK hynix, Western Digital Corporation, and Xilinx is working on a new high-speed interconnect based on a specification due out later this year.

Gen-Z Consortium president Kurtis Bowman, who is also the director of server solutions in the office of the CTO at Dell EMC, says that specification will then be used to create a new open memory interconnect in the form of a proof-of-concept in 2017. Production of the new memory connect would then move forward in 2018, resulting in servers using that memory bus most likely arriving by 2020, says Bowman.

Capable of supporting several hundred GB/s of bandwidth to provide access to sub-100 nanosecond memory such as the 3D X Point memory technology that Intel and Micron are developing, the memory interconnect technology being proposed by the Gen-Z consortium is at the very least intriguing because it provides a crucial missing piece in the quest to shrink the data center.

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